Using existing technology, the reconfigurable computer paradigm cannot be realized with high enough efficiency to be viable for many important applications such as space borne on-board processors because of the lack of the infrastructure and programming methodologies.
Specifically, conventional computing methods and systems have the following problems:                Existing techniques do not provide an efficient application programming approach that can adequately address the strengths and weaknesses of networked computers based on the use of the reconfigurable computer (RCC) paradigm.        Existing techniques do not provide a standardized interface that allows dissimilar processing functions to be mixed and matched to form complex algorithms in a manner that fosters re-use and programming ease while maximizing processing efficiency.        Existing approaches require that algorithm developers be expert at programming field programmable gate arrays (FPGAs) to achieve good processing efficiency needed for demanding processing applications.        Existing approaches to achieving high efficiency do not foster re-use of technology, which results in higher development costs and longer development time.        Existing approaches to achieving high efficiency are not consistent with well-developed and generally accepted software development methodologies.        Using existing approaches, FPGA system developers may improve either programmability or performance but not both.        While there are commercially available tools that allow certain RCCs to be implemented in high-order languages such as “C,” they do so at the expense of processing efficiency.        
Past solutions have been ad-hoc and have not provided the structures needed to use the RCC paradigm on complex processing applications in a manner that is computationally efficient and economical over the product life cycle. This lack of efficiency precluded the use of the RCC paradigm in applications such as large-scale space-based signal processing where size, weight, and power constraints constitute the main requirements.
The present invention provides a systematic solution for implementing high-performance and efficient super-computer class RCCs. It can achieve both programming ease and high performance simultaneously.